Accelerating multiple query processing operations

ABSTRACT

Embodiments include methods, systems and computer program products a for offloading multiple processing operations to an accelerator includes receiving, by a processing device, a database query from an application. The method also includes performing analysis on the database query and selecting an accelerator template from a plurality of accelerator templates based on the analysis of the database query. The method further includes transmitting an indication of the accelerator template to the accelerator and executing at least a portion of the database query on the accelerator.

This application is a continuation application of the legally related U.S. Ser. No. 13/961,089 filed Aug. 7, 2013, the contents of which are incorporated by reference herein in their entirety.

BACKGROUND

The present invention relates to accelerating multiple query processing operations, and more specifically, to an integrated hardware device for accelerating multiple query processing operations.

Currently, hardware accelerators, such as Field Programmable Gate Arrays (FPGAs), are used to accelerate individual query processing operations. These query processing operations include, but are not limited to, sort operations, decompression operations, predicate evaluation operations, and join operations.

In general, a single database query includes multiple processing operations. In some cases, accelerating only one of the processing operations on an accelerator may not be sufficient to increase the processing speed of the entire database query. For example, the database query may include more than one expensive, or time consuming, processing operation. In addition, the overhead cost incurred by the interface between an accelerator and a host may not be justified by accelerating only one of the query processing operations.

SUMMARY

According to an embodiment, a method for offloading multiple processing operations to an accelerator includes receiving, by a processing device, a database query from an application. The method also includes performing analysis on the database query and selecting an accelerator template from a plurality of accelerator templates based on the analysis of the database query. The method further includes transmitting an indication of the accelerator template to the accelerator and executing at least a portion of the database query on the accelerator.

According to another embodiment, a system for offloading multiple processing operations to an accelerator includes a processing device configured to receive a database query from an application. The processor is also configured to perform analysis on the database query and to select an accelerator template from a plurality of accelerator templates based on the analysis of the database query. The system also includes an accelerator configured to receive an indication of the accelerator template from the processing device and to execute at least a portion of the database query.

According to another embodiment, a computer program product including a non-transitory computer readable storage medium having computer readable program code stored thereon that, when executed, performs a method. The method includes receiving a database query from an application. The method also includes performing analysis on the database query and selecting an accelerator template from a plurality of accelerator templates based on the analysis of the database query. The method further includes transmitting an indication of the accelerator template to the accelerator and executing at least a portion of the database query on the accelerator.

Additional features and advantages are realized through the techniques of the present invention. Other embodiments and aspects of the invention are described in detail herein and are considered a part of the claimed invention. For a better understanding of the invention with the advantages and the features, refer to the description and to the drawings.

BRIEF DESCRIPTION OF THE SEVERAL VIEWS OF THE DRAWINGS

The subject matter which is regarded as the invention is particularly pointed out and distinctly claimed in the claims at the conclusion of the specification. The forgoing and other features, and advantages of the invention are apparent from the following detailed description taken in conjunction with the accompanying drawings in which:

FIG. 1 depicts a block diagram of a computer system for practicing the teachings herein according to an embodiment;

FIG. 2 depicts a block diagram of a system for accelerating multiple query processing operations in accordance with an exemplary embodiment;

FIG. 3 depicts a block diagram of a system having an integrated hardware device for accelerating multiple query processing operations in accordance with an exemplary embodiment; and

FIG. 4 depicts a flow diagram of a method for accelerating multiple query processing operations in accordance with an exemplary embodiment.

DETAILED DESCRIPTION

Embodiments disclosed herein include methods, systems and computer program products for accelerating multiple query processing operations. In exemplary embodiments, a method of offloading multiple processing operations within a query to a single accelerator and effective pipelining the different operations on the accelerator is provided. In exemplary embodiments, accelerating multiple operations in a single accelerator reduces the interfacing overhead among operations and between accelerator and host.

In exemplary embodiments, acceleration of different database query operations is performed on the accelerator in a parallel/pipelined fashion. Offloading multiple processing operations to a single accelerator results in increased end-to-end performance of the database query. For example, the performance is improved by acceleration of a larger portion of the database query, as well as better amortization of the setup, teardown and data transfer overhead between the host and the accelerator. Moreover, pipelining these operations on the accelerator provides the acceleration of multiple functions with improved overall query processing throughput on the accelerator.

Referring now to FIG. 1, a block diagram of an exemplary computer system 100 for use with the teachings herein is shown. The methods described herein can be implemented in hardware software (e.g., firmware), or a combination thereof. In an exemplary embodiment, the methods described herein are implemented in hardware, and is part of the microprocessor of a special or general-purpose digital computer, such as a personal computer, workstation, minicomputer, or mainframe computer. The system 100 therefore includes general-purpose computer 101.

In an exemplary embodiment, in terms of hardware architecture, as shown in FIG. 1, the computer 101 includes a processor 105, memory 110 coupled via a memory controller 115, a storage device 120, and one or more input and/or output (I/O) devices 140, 145 (or peripherals) that are communicatively coupled via a local input/output controller 135. The input/output controller 135 can be, for example, but not limited to, one or more buses or other wired or wireless connections, as is known in the art. The input/output controller 135 may have additional elements, which are omitted for simplicity, such as controllers, buffers (caches), drivers, repeaters, and receivers, to enable communications. Further, the local interface may include address, control, and/or data connections to enable appropriate communications among the aforementioned components. The storage device 120 may include one or more hard disk drives (HDDs), solid state drives (SSDs), or any other suitable form of storage.

The processor 105 is a computing device for executing hardware instructions or software, particularly that stored in memory 110. The processor 105 can be any custom made or commercially available processor, a central processing unit (CPU), an auxiliary processor among several processors associated with the computer 101, a semiconductor based microprocessor (in the form of a microchip or chip set), a macroprocessor, or generally any device for executing instructions. The processor 105 may include a cache 170, which may be organized as a hierarchy of more cache levels (L1, L2, etc.).

The memory 110 can include any one or combination of volatile memory elements (e.g., random access memory (RAM, such as DRAM, SRAM, SDRAM, etc.)) and nonvolatile memory elements (e.g., ROM, erasable programmable read only memory (EPROM), electronically erasable programmable read only memory (EEPROM), programmable read only memory (PROM), tape, compact disc read only memory (CD-ROM), disk, diskette, cartridge, cassette or the like, etc.). Moreover, the memory 110 may incorporate electronic, magnetic, optical, and/or other types of storage media. Note that the memory 110 can have a distributed architecture, where various components are situated remote from one another, but can be accessed by the processor 105.

The instructions in memory 110 may include one or more separate programs, each of which comprises an ordered listing of executable instructions for implementing logical functions. In the example of FIG. 1, the instructions in the memory 110 include a suitable operating system (OS) 111. The operating system 111 essentially controls the execution of other computer programs and provides scheduling, input-output control, file and data management, memory management, and communication control and related services.

In an exemplary embodiment, a conventional keyboard 150 and mouse 155 can be coupled to the input/output controller 135. Other output devices such as the I/O devices 140, 145 may include input devices, for example but not limited to a printer, a scanner, microphone, and the like. Finally, the I/O devices 140, 145 may further include devices that communicate both inputs and outputs, for instance but not limited to, a network interface card (NIC) or modulator/demodulator (for accessing other files, devices, systems, or a network), a radio frequency (RF) or other transceiver, a telephonic interface, a bridge, a router, and the like. The system 100 can further include a display controller 125 coupled to a display 130. In an exemplary embodiment, the system 100 can further include a network interface 160 for coupling to a network 165. The network 165 can be an IP-based network for communication between the computer 101 and any external server, client and the like via a broadband connection. The network 165 transmits and receives data between the computer 101 and external systems. In an exemplary embodiment, network 165 can be a managed IP network administered by a service provider. The network 165 may be implemented in a wireless fashion, e.g., using wireless protocols and technologies, such as Wi-Fi, WiMax, etc. The network 165 can also be a packet-switched network such as a local area network, wide area network, metropolitan area network, Internet network, or other similar type of network environment. The network 165 may be a fixed wireless network, a wireless local area network (LAN), a wireless wide area network (WAN) a personal area network (PAN), a virtual private network (VPN), intranet or other suitable network system and includes equipment for receiving and transmitting signals.

If the computer 101 is a PC, workstation, intelligent device or the like, the instructions in the memory 110 may further include a basic input output system (BIOS) (omitted for simplicity). The BIOS is a set of essential routines that initialize and test hardware at startup, start the OS 111, and support the transfer of data among the storage devices. The BIOS is stored in ROM so that the BIOS can be executed when the computer 101 is activated.

When the computer 101 is in operation, the processor 105 is configured to execute instructions stored within the memory 110, to communicate data to and from the memory 110, and to generally control operations of the computer 101 pursuant to the instructions. In exemplary embodiments, the computer system 100 includes one or more accelerators 180 that are configured to communicate with the processor 105. The accelerator 180 may be a field programmable gate array (FPGA) or other suitable device that is configured to perform specific processing tasks. In exemplary embodiments, the computer system 100 may be configured to offload certain processing tasks to an accelerator 180 because the accelerator 180 can perform the processing tasks more efficiently than the processor 105.

Referring now to FIG. 2, a block diagram illustrating a system 200 having an accelerator 206 for accelerating multiple query processing operations in accordance with an exemplary embodiment is shown. The system 200 includes a host 204, which may be a computer as shown in FIG. 1 having a central processing unit configured to execute database management software. In exemplary embodiments, the host 204 receives queries from an application 202 and responsively offloads one or more query processing operations to the accelerator 206. In exemplary embodiments, the accelerator 206 is an integrated hardware device. For example, the accelerator 206 may be a FPGA.

Referring now to FIG. 3, a block diagram illustrating a system 300 having an integrated hardware device 350 for accelerating multiple query processing operations in accordance with an exemplary embodiment is shown. In exemplary embodiments, the host 310 includes a query optimizer 312, which receives a query from an application and performs analysis on the query. Based on the analysis of the query, the query optimizer 312 selects an accelerator template from a plurality of accelerator templates. In exemplary embodiments, each of the plurality of accelerator templates is a stored processing configuration that the integrated hardware device 350 is capable of executing. Once the query optimizer 312 selects an accelerator template, the acceleration coordinator 314 transmits a signal to the integrated hardware device 350, which causes the integrated hardware device 350 to implement the selected template.

In exemplary embodiments, the system 300 also includes a storage device 320 that is accessed by the host 310. The storage device 320 is configured to store database data and to provide data pages 322 to the host 310. The host 310 is configured to provide the data page addresses for the input and output pages 322 to the integrated hardware device 350. In exemplary embodiments, database pages 322 are brought into the integrated hardware device 350 via input direct memory access and output pages are sent back to the host 310 via output direct memory access.

In exemplary embodiments, the host 310 may execute certain query operations 316 and the integrated hardware device 350 operates in parallel to reduce the response time to the application 302. The host 310 feeds a block of data, the data pages 322, to the integrated hardware device 350 to begin processing and continues to retrieve data from the storage device 320. In exemplary embodiments, the integrated hardware device 350 is configured to store processed data in output buffer and to continue processing as long as there is data being input. In exemplary embodiments, the integrated hardware device 350 manages both tasks of pulling input data from the host 310 and returning the output data to the host 310. The host 310 may be configured to execute various query operations 316 that are not offloaded to the integrated hardware device 350.

In exemplary embodiments, each of the accelerator templates includes a plurality of acceleration modules that each correspond to different database functions. For example, the acceleration modules may include, but are not limited to, a row extraction module, a decompression module, an evaluation module, a projection module, a sort module and a formatting module. In exemplary embodiments, the integrated hardware device 350 is capable of executing a plurality of acceleration templates. The number and configuration of the acceleration modules present in each acceleration template is selected based on the functionality required by the query operations that are offloaded to the integrated hardware device 350.

In exemplary embodiments, the acceleration modules are arranged on the integrated hardware device 350 in a feed-forward pipelined fashion, with each acceleration module feeding into the next acceleration module. In exemplary embodiments, different acceleration modules can have different data processing rates. In order to maintain continuous data flow and minimize stalls, multiple slower acceleration modules may be operated in parallel in order to be rate-matched with the faster acceleration modules. In addition, intermediate buffers may be disposed between acceleration modules in the pipelined configuration.

Continuing with reference to FIG. 3, the integrated hardware device 350 is configured with an accelerator template that includes a plurality of acceleration modules, which include a row extraction module 352, a decompression module 354, a predicate evaluation module 356, a projection module 358, a sort module 360 and a formatting module 362. In addition, the accelerator template includes one or more buffers 364. In exemplary embodiments, the query optimizer 312 on the host 310 selects an accelerator template having a number and configuration of the acceleration modules based on the functionality required by the query operations that are offloaded to the integrated hardware device 350.

Referring now to FIG. 4, a flow diagram illustrating a method 400 for offloading multiple processing operations to a single accelerator according to an embodiment is shown. As shown at block 402, the method 400 includes receiving a database query from an application. Next, as shown at block 404, the method 400 includes performing analysis on the query and selecting an accelerator template from a plurality of accelerator templates based on the analysis. In exemplary embodiments, each of the plurality of accelerator templates has a configuration of accelerator modules which are configured to efficiently execute various query operations. As shown at block 406, the method 400 includes transmitting an indication of the accelerator template to the accelerator. In exemplary embodiments, the accelerator is a FPGA that is capable of being configured to execute each of the plurality of accelerator templates. Next, the accelerator executes at least a portion of the query, as shown at block 408.

As will be appreciated by one skilled in the art, aspects of the present invention may be embodied as a system, method or computer program product. Accordingly, aspects of the present invention may take the form of an entirely hardware embodiment, an entirely software embodiment (including firmware, resident software, micro-code, etc.) or an embodiment combining software and hardware aspects that may all generally be referred to herein as a “circuit,” “module” or “system.” Furthermore, aspects of the present invention may take the form of a computer program product embodied in one or more computer readable medium(s) having computer readable program code embodied thereon.

Any combination of one or more computer readable medium(s) may be utilized. The computer readable medium may be a computer readable storage medium. A computer readable storage medium may be, for example, but not limited to, an electronic, magnetic, optical, electromagnetic, infrared, or semiconductor system, apparatus, or device, or any suitable combination of the foregoing. More specific examples (a non-exhaustive list) of the computer readable storage medium would include the following: an electrical connection having one or more wires, a portable computer diskette, a hard disk, a random access memory (RAM), a read-only memory (ROM), an erasable programmable read-only memory (EPROM or Flash memory), an optical fiber, a portable compact disc read-only memory (CD-ROM), an optical storage device, a magnetic storage device, or any suitable combination of the foregoing. In the context of this document, a computer readable storage medium may be any tangible medium that can contain, or store a program for use by or in connection with an instruction execution system, apparatus, or device.

Program code embodied on a computer readable medium may be transmitted using any appropriate medium, including but not limited to wireless, wireline, optical fiber cable, RF, etc., or any suitable combination of the foregoing.

Computer program code for carrying out operations for aspects of the present invention may be written in any combination of one or more programming languages, including an object oriented programming language such as Java, Smalltalk, C++ or the like and conventional procedural programming languages, such as the “C” programming language or similar programming languages. The program code may execute entirely on the user's computer, partly on the user's computer, as a stand-alone software package, partly on the user's computer and partly on a remote computer or entirely on the remote computer or server. In the latter scenario, the remote computer may be connected to the user's computer through any type of network, including a local area network (LAN) or a wide area network (WAN), or the connection may be made to an external computer (for example, through the Internet using an Internet Service Provider).

Aspects of the present invention are described above with reference to flowchart illustrations and/or block diagrams of methods, apparatus (systems) and computer program products according to embodiments of the invention. It will be understood that each block of the flowchart illustrations and/or block diagrams, and combinations of blocks in the flowchart illustrations and/or block diagrams, can be implemented by computer program instructions. These computer program instructions may be provided to a processor of a general purpose computer, special purpose computer, or other programmable data processing apparatus to produce a machine, such that the instructions, which execute via the processor of the computer or other programmable data processing apparatus, create means for implementing the functions/acts specified in the flowchart and/or block diagram block or blocks.

These computer program instructions may also be stored in a computer readable medium that can direct a computer, other programmable data processing apparatus, or other devices to function in a particular manner, such that the instructions stored in the computer readable medium produce an article of manufacture including instructions which implement the function/act specified in the flowchart and/or block diagram block or blocks.

The computer program instructions may also be loaded onto a computer, other programmable data processing apparatus, or other devices to cause a series of operational steps to be performed on the computer, other programmable apparatus or other devices to produce a computer implemented process such that the instructions which execute on the computer or other programmable apparatus provide processes for implementing the functions/acts specified in the flowchart and/or block diagram block or blocks.

The disclosed flowchart and block diagrams illustrate the architecture, functionality, and operation of possible implementations of systems, methods and computer program products according to various embodiments of the present invention. In this regard, each block in the flowchart or block diagrams may represent a module, segment, or portion of code, which comprises one or more executable instructions for implementing the specified logical function(s). It should also be noted that, in some alternative implementations, the functions noted in the block may occur out of the order noted in the figures. For example, two blocks shown in succession may, in fact, be executed substantially concurrently, or the blocks may sometimes be executed in the reverse order, depending upon the functionality involved. It will also be noted that each block of the block diagrams and/or flowchart illustration, and combinations of blocks in the block diagrams and/or flowchart illustration, can be implemented by special purpose hardware-based systems that perform the specified functions or acts, or combinations of special purpose hardware and computer instructions.

The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the invention. As used herein, the singular forms “a”, “an” and “the” are intended to include the plural forms as well, unless the context clearly indicates otherwise. It will be further understood that the terms “comprises” and/or “comprising,” when used in this specification, specify the presence of stated features, integers, steps, operations, elements, and/or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, element components, and/or groups thereof.

The corresponding structures, materials, acts, and equivalents of all means or step plus function elements in the claims below are intended to include any structure, material, or act for performing the function in combination with other claimed elements as specifically claimed. The description of the present invention has been presented for purposes of illustration and description, but is not intended to be exhaustive or limited to the invention in the form disclosed. Many modifications and variations will be apparent to those of ordinary skill in the art without departing from the scope and spirit of the invention. The embodiment was chosen and described in order to best explain the principles of the invention and the practical application, and to enable others of ordinary skill in the art to understand the invention for various embodiments with various modifications as are suited to the particular use contemplated.

The flow diagrams depicted herein are just one example. There may be many variations to this diagram or the steps (or operations) described therein without departing from the spirit of the invention. For instance, the steps may be performed in a differing order or steps may be added, deleted or modified. All of these variations are considered a part of the claimed invention.

While the preferred embodiment to the invention had been described, it will be understood that those skilled in the art, both now and in the future, may make various improvements and enhancements which fall within the scope of the claims which follow. These claims should be construed to maintain the proper protection for the invention first described. 

What is claimed is:
 1. A method for accelerating multiple query processing operations on a processor comprising: selecting a plurality of accelerator templates based on an analysis of a database query, wherein each of the plurality of accelerator templates comprises, a row extraction module, a decompression module, a predicate evaluation module, a projection module, a sort module, and a formatting module; wherein each of the plurality of templates is a stored processing configuration that an accelerator is configured to execute, wherein a particular number of selected acceleration templates is selected based on a functionality required by the query operations to be offloaded to an accelerator; transmitting an indication of the accelerator template to the accelerator; configuring a processing configuration of the accelerator based on the accelerator template selected, wherein each of the plurality of accelerator templates includes a plurality of pipelined acceleration modules arranged on an integrated hardware device in a feed-forward pipelined fashion, such that each of the different acceleration modules can have different data processing rates; and executing at least a portion of the database query on the accelerator, wherein during the execution of the at least a portion of the database query on the accelerator, the accelerator manages a pulling of input data from a host device and returning an output data to the host device.
 2. The method of claim 1, wherein the accelerator template comprises a configuration of a plurality of accelerator modules that are configured to efficiently execute the portion of the database query.
 3. The method of claim 2, wherein the plurality of accelerator modules comprises: a join module; and an aggregation module.
 4. The method of claim 2, wherein the accelerator template further comprises one or more buffers.
 5. The method of claim 1, wherein the accelerator is a field programmable gate array.
 6. The method of claim 1, wherein at least a second portion of the database query is executed by the processing device.
 7. The method of claim 1, wherein each of the plurality of accelerator templates comprises a configuration of accelerator modules configured to efficiently execute different database query operations. 